With the recent demand for very highly integrated circuit devices, copper has become more widely used as a wiring and/or plug material. Copper has the advantageous characteristics of lower resistance and superior electromigration resistance, as compared to aluminum, which has enjoyed wide use up to now.
However, as miniaturization of device elements has progressed, electromigration (hereinafter referred to as “EM”) has become a problem even for wiring made from copper. A copper wiring is typically formed from a copper film formed by a plating method, or the like. In such a case, a resulting copper film has a polycrystalline-structure of aggregate copper grains. If a voltage is applied across a copper wiring having this type of structure, a mass transfer occurs via grain boundaries of the copper grains. As a result, EM can occur.
In wiring having a small width, the size of copper grains becomes small. Consequently, EM problems from mass transfer through such grain boundaries can be very pronounced. Several investigations have been undertaken that mix silver with copper in wirings to try to resolve the EM problem.
Wirings made from copper alloys containing silver, niobium, or aluminum oxide (Al2O3) are disclosed in Japanese Patent Application Publication 11-204524A. For such approaches, it is preferable that the amount of silver within the wiring be equal to or less than 1% by mass, and that the amount of niobium is equal to or less than 0.4% by mass, for example. If the amount of silver or niobium is made equal to or higher than the amounts set forth above, an alloy phase can precipitate locally within the wiring that has silver or niobium as its main constituent. Such a phase can result in undesirable differences in the electrical conductivity of the wiring.
Wirings made of copper alloys containing silver (Ag), arsenic (As), bismuth (Bi), phosphorous (P), antimony (Sb), silicon (Si), or titanium (Ti) are reported in Japanese Patent Publication JP 2000-349085A. In the publication, the amount of Ag, As, Bi, P, Sb, Si, or Ti within a wiring is equal to or greater than 0.1% by mass, and less than the maximum solid solubility limit for the element. It is considered that if an amount of silver added to copper is equal to or greater than the maximum solid solubility limit, a portion of the silver does not alloy, but precipitates out. Thus, a resulting conductivity can be lowered.
Recently, the development of stress migration in copper wirings has become a problem. FIGS. 11(a) and 11(b) are cross sectional views of multi-layer copper wirings formed by a damascene method. In such a structure, an upper layer wiring 121b is connected to an upper portion of a lower layer wiring 121a. An upper layer wiring 121b includes a connection plug and a wiring formed on an upper portion thereof.
Due to stress migration of copper in this type of multi-layer copper wiring, a void 122a (shown in FIG. 11(a)) or a void 122b (shown in FIG. 11(b)) may develop at an interface between a lower layer wiring 121a and an upper layer wiring 121b. Such voids can cause connection failures between wirings, lowering yields of the semiconductor device. Further, such semiconductor devices can become unstable over long-term use.
Void 122a can develop in the upper layer wiring 121b side as shown in FIG. 11(a). That is, the void 122a develops in a portion of the connection plug constituting the upper layer wiring 121b. It is thought that this type of void 122a develops due to the occurrence of copper “shrinkage” within the upper layer wiring 121b, resulting in copper migrating upward within connection plug. This type of void 122a develops very conspicuously in high-temperature heat treatment cycles.
On the other hand, void 122b develops in an upper surface of lower layer wiring 121a in FIG. 11(b). This type of void 122b is thought to be developed by the accumulation of defects due to copper diffusion at surfaces of the lower layer wiring 121a contacting the connection plug portion of the upper layer wiring 121b. 
In accordance with an investigation by the inventors of the present invention, it has been discovered that the type of cavitation (e.g., void) phenomena noted above occurs conspicuously around the temperature of approximately 150° C. Unfortunately, this is a temperature that a semiconductor device commonly experiences (for example during a bonding process, photoresist baking process, or the like).
The development of such above-mentioned voids 122a and 122b can be the cause of connection failures that develop between a connection plug and wiring. This can result in reductions in yield of such semiconductor devices, or long term instability in the operation of such semiconductor devices.
As noted above, voids 122a and 122b are believed to be caused by internal stress that develops within copper wiring due to thermal cycles imparted by semiconductor processing and the like. Thus, in addition to improving yields and reducing instability in a semiconductor device, the prevention of voids can have other stress reduction related advantages. In particular, the prevention of voids like 122a can be effective in suppressing deformation of an overall wiring. Further, the prevention of voids like 122b can increase the material strength of the surface of the wiring.
From the above it is understood that materials utilized in forming metallic regions such as wirings, along with processing steps, must be considered in order to suppress the development of these types of stress migration and corresponding deleterious effects.
In addition, in recent years there has been a demand for higher level characteristics in the operation of elements of a semiconductor device. As a result there is a need for the development of materials, such as those used for wirings that show high-speed operation characteristics that can exceed those of conventional copper wirings.
In light of the above, it would be desirable to arrive at semiconductor device having a metallic region that has increased resistance to stress migration, and/or increased reliability as compared to the above mentioned conventional approaches. In addition, it would be desirable to provide a process that can manufacture such a semiconductor device in a stable fashion.